vishay siliconix si2323ds document number: 72024 s09-0133-rev. d, 02-feb-09 www.vishay.com 1 p-channel 20-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 available ? trenchfet ? power mosfet applications ? load switch ? pa switch product summary v ds (v) r ds(on) ( )i d (a) - 20 0.039 at v gs = - 4.5 v - 4.7 0.052 at v gs = - 2.5 v - 4.1 0.068 at v gs = - 1.8 v - 3.5 g s d to p v i ew 2 3 to-236 (sot-23) 1 si2323ds (d3)* * marking code ordering information: si2323ds-t1 si2323ds-t1-e3 (lead (pb)-free) si2323ds-t1-ge3 (lead (pb)-free and halogen-free) notes: a. surface mounted on 1" x 1" fr4 board. b. pulse width limited by maximum junction temperature. * pb containing terminations are not rohs compliant, exemptions may apply. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 5 s steady state unit drain-source voltage v ds - 20 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) a, b t a = 25 c i d - 4.7 - 3.7 a t a = 70 c - 3.8 - 2.9 pulsed drain current i dm - 20 continuous source current (diode conduction) a, b i s - 1.0 - 0.6 maximum power dissipation a, b t a = 25 c p d 1.25 0.75 w t a = 70 c 0.8 0.48 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 5 s r thja 75 100 c/w steady state 120 166 maximum junction-to-foot (drain) steady state r thjf 40 50
www.vishay.com 2 document number: 72024 s09-0133-rev. d, 02-feb-09 vishay siliconix si2323ds notes: a. pulse test: pw 300 s, duty cycle 2 %. b. for design aid only, not subject to production testing. c. switching time is essentially independent of operating temperature. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions limits unit min. typ. max. static drain-source breakdown voltage v (br)dss v gs = 0 v, i d = - 250 a - 20 v gate-threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.40 - 1.0 gate-body leakage i gss v ds = 0 v, v gs = 8 v 100 na zero gate voltage drain current i dss v ds = - 16 v, v gs = 0 v - 1 a v ds = - 16 v, v gs = 0 v, t j = 55 c - 10 on-state drain current a i d(on) v ds - 5 v, v gs = - 4.5 v - 20 a drain-source on-resistance a r ds(on) v gs = - 4.5 v, i d = - 4.7 a 0.031 0.039 v gs = - 2.5 v, i d = - 4.1 a 0.041 0.052 v gs = - 1.8 v, i d = - 2.0 a 0.054 0.068 forward transconductance a g fs v ds = - 5 v, i d = - 4.7 a 16 s diode forward voltage v sd i s = - 1.0 a, v gs = 0 v - 0.7 - 1.2 v dynamic b total gate charge q g v ds = - 10 v, v gs = - 4.5 v i d ? - 4.7 a 12.5 19 nc gate-source charge q gs 1.7 gate-drain charge q gd 3.3 input capacitance c iss v ds = - 10 v, v gs = 0 v, f = 1 mhz 1020 pf output capacitance c oss 191 reverse transfer capacitance c rss 140 switching c tu r n - o n t i m e t d(on) v dd = - 10 v, r l = 10 i d ? - 1.0 a, v gen = - 4.5 v r g = 6 25 40 ns t r 43 65 turn-off time t d(off) 71 110 t f 48 75
document number: 72024 s09-0133-rev. d, 02-feb-09 www.vishay.com 3 vishay siliconix si2323ds typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 4 8 12 16 20 012345 v gs = 5 thru 2.5 v 1 v 1.5 v v ds - drain-to-source voltage (v) - drain current (a) i d 2 v 0.00 0.03 0.06 0.09 0.12 0.15 0 4 8 121620 v gs = 4.5 v v gs = 2.5 v - on-resistance ( ) r ds(on) i d - drain current (a) v gs = 1.8 v 0 1 2 3 4 5 03691215 v ds = 6 v i d = 4.7 a - gate-to-source voltage (v) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 4 8 12 16 20 0.0 0.5 1.0 1.5 2.0 2.5 25 c 125 c v gs - gate-to-source voltage (v) - drain current (a) i d t c = - 55 c 0 300 600 900 1200 1500 1800 048121620 c rss c oss c iss v ds - drain-to-source voltage (v) c - capacitance (pf) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 4.7 a t j - junction temperature (c) (normalized) - on-resistance r ds(on)
www.vishay.com 4 document number: 72024 s09-0133-rev. d, 02-feb-09 vishay siliconix si2323ds typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 1.0 1.2 0.1 10 20 0.0 0.2 0.4 0.6 0.8 t j = 150 c v sd - source-to-drain voltage (v) - source current (a) i s 1 t j = 25 c - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 140 a variance (v) v gs(th) t j - temperature (c) on-resistance vs. gate-to-source voltage single pulse power 0.00 0.03 0.06 0.09 0.12 0.15 012345 i d = 4.7 a - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) i d = 2 a 0.01 0 1 6 12 2 4 10 600 0.1 power (w) time (s) 8 10 100 t a = 25 c safe operating area 100 1 0.1 1 10 100 0.01 10 t a = 25 c single pulse - drain current (a) i d p(t) = 10 dc 0.1 i d(on) limited r ds(on) * limited by bvdss limited p(t) = 1 p(t) = 0.1 p(t) = 0.01 p(t) = 0.001 p(t) = 0.0001 i dm limited v ds - drain-to-source voltage (v) *v gs > minimum v gs at which r ds(on) is specified
document number: 72024 s09-0133-rev. d, 02-feb-09 www.vishay.com 5 vishay siliconix si2323ds typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72024 . normalized thermal transient impedance, junction-to-ambient square wave pulse duration (s) normalized effective transient thermal impedance 2 1 0.1 0.01 10 -3 10 -2 1 10 600 10 -1 10 -4 duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse 100 1. duty cycle, d = 2. per unit base = r thja = 120 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm
vishay siliconix package information document number: 71196 09-jul-01 www.vishay.com 1 sot-23 (to-236): 3-lead b e e 1 1 3 2 s e e 1 d a 2 a a 1 c s e a ting pl a ne 0.10 mm 0.004" c c l 1 l q g au ge pl a ne s e a ting pl a ne 0.25 mm dim millimeters inches min max min max a 0.89 1.12 0.0 3 5 0.044 a 1 0.01 0.10 0.0004 0.004 a 2 0.88 1.02 0.0 3 46 0.040 b 0. 3 5 0.50 0.014 0.020 c 0.085 0.18 0.00 3 0.007 d 2.80 3 .04 0.110 0.120 e 2.10 2.64 0.08 3 0.104 e 1 1.20 1.40 0.047 0.055 e 0.95 bsc 0.0 3 74 ref e 1 1.90 bsc 0.0748 ref l 0.40 0.60 0.016 0.024 l 1 0.64 ref 0.025 ref s 0.50 ref 0.020 ref q 3 8 3 8 ecn: s-0 3 946-rev. k, 09-jul-01 dwg: 5479
an807 vishay siliconix document number: 70739 26-nov-03 www.vishay.com 1 mounting little foot sot-23 power mosfets wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ), for the basis of the pad design for a littl e foot sot-23 power mosfet footprint . in converting this footprint to the pad set for a power device, designers must make tw o connections: an electrical connection and a thermal connection, to draw heat away from the package. the electrical connections for the sot-23 are very simple. pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. as in the other little foot packages, the drai n pin serves the additional function of providing the thermal connection from the package to the pc board. the total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. also, heat spreads in a circular fashion from the heat source. in this case the drain pin is the heat source when looking at heat spread on the pc board. figure 1 shows the footprint with copper spreading for the sot-23 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copper over lies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the ambient air. this pattern uses all the available area underneath the body for this purpose. figure 1. footprint with copper spreading 0.114 2.9 0.059 1.5 0.0394 1.0 0.037 0.95 0.150 3.8 0.081 2.05 since surface-mounted packages are small, and reflow soldering is the most common way in whic h these are affixed to the pc board, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device.
application note 826 vishay siliconix document number: 72609 www.vishay.com revision: 21-jan-08 25 application note recommended minimum pads for sot-23 0.106 (2.692) recommended mi nimum pads dimensions in inches/(mm) 0.022 (0.559) 0.049 (1.245) 0.029 (0.724) 0.037 (0.950) 0.053 (1.341) 0.097 (2.459) return to index return to index
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